Advances in semiconductor manufacturing technology have resulted in, among other things, reducing the cost of sophisticated electronics to the extent that integrated circuits have become ubiquitous in the modern environment.
As is well-known, integrated circuits are typically manufactured in batches, and these batches usually contain a plurality of semiconductor wafers within and upon which integrated circuits are formed through a variety of semiconductor manufacturing steps, including, for example, depositing, masking, patterning, implanting, etching, and so on.
Completed wafers are tested to determine which die, or integrated circuits, on the wafer are capable of operating according to predetermined specifications. In this way, integrated circuits that cannot perform as desired are not packaged, or otherwise incorporated into finished products.
It is a common practice to use several different test system set-ups in order to test the wafers. Sometimes different test environments are required for low temperature, room temperature, and high temperature testing of the circuits on a wafer. Additionally, different test systems may be used for Built-In Self Test (BIST) style testing, and for application of conventional functional test patterns. Consequently, there is a variety of test equipment for wafer level testing which must be calibrated and verified.
Presently, a number of individual analytical and/or repair tools are required to evaluate the performance, of the various constituent apparatus of wafer sort and wafer burn-in systems. None of these analytical or repair tools emulate closely the actual production configuration of the wafer-level test apparatus.
What is needed are methods and apparatus for calibrating and verifying various wafer level test systems while these test systems are configured closely to their actual production usage configurations.